Advances in computer network communication and switching provide an improved experience for users who wish to store, retrieve and use information. The advent of a number of communication technologies has proven very useful to society, but the interoperability of these technologies has become an engineering challenge. There is a strong desire to support past, present and future device interoperability, and to improve the efficiency, use and deployment of circuits and systems in the electronics marketplace. The present invention provides useful novel techniques for achieving these goals.
One of the high-speed communications technologies that has been employed in electronic circuits is a serializer-deserializer, or SerDes, which supports the serial communication between circuits while using a parallel internal bus. FIG. 1 depicts a SerDes implementation according to the prior art. Chip A and Chip B both include internal circuitry that employs parallel communication and logical functions (e.g. arithmetic functions, memory functions, etc.). However, Chip A and Chip B communicate with one another over a serial communication link. The SerDes A and SerDes B convert the parallel communication from an internal n-bit bus to a serial data stream complete with data portions that signify the beginning of a communication sequence, the data itself, and the end of the communication sequence, etc. Likewise, the SerDes also serve to decode the serial data received on the recive side. A number of SerDes formats are used in the industry, but each often requires its own hardware design and therefore can only talk to another circuit that employs a similar SerDes interface.
What is needed is a circuit with the ability to communicate using a number of different communications protocols.